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Published in:   Vol. 8 Issue 1 Date of Publication:   June 2019

An Efficient Majority Error Detection in Logic Decoding with Euclidean Geometry Low Density Parity Check (Eg-Ldpc) Codes

M .Vengadapathiraj,U.Maheswaran, A.Karunakaran

Page(s):   09-11 ISSN:   2278-2397
DOI:   10.20894/IJBI.105.008.001.003 Publisher:   Integrated Intelligent Research (IIR)


  1. Myron Flickner,   "Radiation-induced soft errors in advanced semiconductor technologies",   IEEE Trans. Device Mater. Reliab   ,Vol.5   ,Issue 3
    View Artical

  2. R. C. Baumann,   "Models and algorithmic limits for an ECC-based approach to hardening sub-100-nm SRAMs",   IEEE Trans. Nucl. Sci   ,Vol.54   ,Issue 4   ,2005
    View Artical

  3. M. A. Bajura, Y. Boulghassoul, R. Naseer, S. DasGupta, A. F. Witulski, J. Sondeen, S. D. Stansberry, J. Draper, L. W. Massengill, and J. N.Damoulakis,   "DEC ECC design to improve memory reliability in sub-100 nm technologies",   Proc. IEEE ICECS
    View Artical

  4. R. Naseer and J. Draper,   "Dynamic low-density parity check codes for fault-tolerant nano-scale memory",   presented at the Foundations Nanosci. (FNANO), Sno   ,2008
    View Artical

  5. S. Ghosh and P. D. Lincoln,   "Low-density parity check codes for error correction in nanoscale memory",   SRI Computer Science Lab., MenloPark, CA, Tech. Re   ,2007
    View Artical

  6. S. Ghosh and P. D. Lincoln,   "Fault secures encoder and decoder for memory applications",   in Proc. IEEE Int. Symp. Defect Fault Toler.VLSI S   ,2007
    View Artical

  7. H. Naeimi and A. DeHon,   "An information theoretical framework for analysis and design of nanoscale fault-tolerant memories ba   ,Vol.54   ,Issue 11   ,2007
    View Artical

  8. B. Vasic and S. K. Chilappagari,   "Fault secure encoder and decoder for nanomemory applications",   IEEE Trans. Very Large Scale Integr   ,Vol.17   ,Issue 4   ,2007
    View Artical

  9. H. Naeimi and A. DeHon,   "Efficient majority logic fault detection with difference-set codes for memory applications",   IEEETrans. Very Large Scale Integr. (VLSI) Syst   ,Vol.20   ,Issue 1   ,2009
    View Artical

  10. S. Liu, P. Reviriego, and J. Maestro,   "Codes on finite geometries",   IEEE Trans. Inf. Theory   ,Vol.51   ,Issue 2   ,2012
    View Artical

  11. H. Tang, J. Xu, S. Lin, and K. A. S. Abdel-Ghaffar,   "Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) ",   IEEE Trans. Very Large Scale Integration (VLSI) Sy   ,Vol.21   ,Issue 1   ,2005
    View Artical